Digital Hardware Design & VHDL

Structural & Dataflow Logic Synthesis for Arithmetic Logic Units

Computer engineering coursework in digital design: modeling, simulating, and synthesizing structural and dataflow VHDL architectures for multiplexers (mux2, mux4, mux8) and an Arithmetic Logic Unit (ALU).

1. The Engineering Problem

Software engineers interact with CPUs as black boxes executing instructions. Understanding how arithmetic calculations, logic branching, and data bus routing physically happen inside the processor requires designing digital logic circuits in Hardware Description Languages (HDL).

2. What Was Built

A suite of VHDL digital logic designs created for Cairo University Computer Engineering computer architecture coursework. Implemented structural and dataflow architectures for 2-to-1, 4-to-1, and 8-to-1 multiplexers, cascading multiplexer trees, and a multi-operation Arithmetic Logic Unit (ALU) verified in ModelSim.

3. System Architecture & Topology

ASCII Topology

Hardware Register-Transfer Level (RTL) models: VHDL entity/architecture definitions simulated with testbenches in ModelSim.

Input Data Lines (A, B) + Opcode Control Signals
                     |
                     v
   +---------------------------------------+
   |             VHDL ALU CORE             |
   |  - Arithmetic Operations: ADD, SUB    |
   |  - Logic Operations: AND, OR, XOR, NOT|
   |  - Flag Generation: Zero, Carry, Sign |
   +-------------------+-------------------+
                       |
                       v
         Output Result + Status Flags

4. Mohamed's Personal Implementation

Designed structural VHDL implementations by interconnecting smaller sub-components into hierarchical multiplexer trees.

Constructed dataflow architectures using concurrent signal assignments and conditional expressions.

Implemented the ALU entity supporting arithmetic and bitwise logic operations based on instruction opcodes.

Verified timing waveforms and logical correctness using ModelSim testbenches.

5. Engineering Challenges & Solutions

Challenge: Avoiding Hardware Glitches and Unintended Latches

Solution: Strictly maintained complete assignment sensitivity lists and default branches across all conditional case statements in VHDL processes.

Impact: Clean synthesis without inferred latches.

6. Technology Stack

HDL

VHDL (Structural & Dataflow)RTL Design

EDA Tools

ModelSimIntel Quartus Prime LiteDigital Waveform Simulators

7. Verified Outcomes

•Successfully completed Computer Architecture laboratory assignments at Cairo University.
•Built a solid practical foundation for microprocessor design and digital hardware systems.

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